1. Field of the Invention
This invention relates to a semiconductor apparatus including a semiconductor substrate, an island region surrounded by a trench for isolation on the semiconductor substrate, a lateral type MOSFET formed in the island region, and a buffer region disposed around the island region for preventing electrical interference between the MOSFET and other elements.
2. Description of the Related Art
An LDMOS (Lateral Double-diffused MOSFET) is known as a MOSFET having a high withstand voltage. When several high withstand voltage LDMOSes are provided on an identical semiconductor substrate, or when an LDMOS and a logical circuit element are formed on an identical semiconductor substrate as a monolithic IC, a buffer region is conventionally formed at a periphery of the LDMOS to prevent electrical interference from other elements. For instance, FIGS. 1 and 2 show a semiconductor apparatus including such a buffer region.
The semiconductor apparatus shown in FIGS. 1 and 2 is a P channel type LDMOS, and has an SOI structure that is composed of a silicon layer 1 formed on a silicon support substrate 2 through a silicon oxide film 3 as an isolation film. The silicon layer 1 includes a silicon island layer 1a that is isolated from other element formation regions by a trench 4. The trench 4 is filled with a silicon oxide film and polysilicon for isolation. A low impurity concentration electric field relaxation layer 5 is formed in a lower part of the silicon island layer 1a contacting the silicon oxide film 3. The impurity concentration of the electric field relaxation layer 5 is controlled to be extremely small so that the relaxation layer 5 substantially functions as an intrinsic semiconductor.
A drift layer 6 composed of a P.sup.- layer is formed in an upper part of the silicon island layer 1a with a low impurity concentration, which is higher than that of the electric field relaxation layer 5. A drain contact layer 7 composed of a P.sup.+ layer is formed in a surface portion of the drift layer 6, and a drain electrode 7a is formed on the drain contact layer 7.
An annular N-well 8a extending into the electric field relaxation layer 5 and an annular channel N-well 8b are concentrically formed around the drain contact layer 7 in the silicon island layer 1a. The N-well 8b is self-aligned relative to a gate polysilicon 9. An annular source diffusion layer 10 (P.sup.+ layer) as a source region and an annular source diffusion layer 11 (N.sup.+ layer) for fixing an electrical potential are formed in the N-well 8b. Further, a gate electrode 9a is disposed on the gate polysilicon 9, and a source electrode 10a is disposed on the source diffusion layers 10, 11. The drain electrode 7a, the gate electrode 9a, and the source electrode 10a are made of a first aluminum. As shown in FIG. 2, a part of the source electrode 10a is notched and the gate electrode 9a is electrically taken out through the notched portion.
Further, a LOCOS oxide film 12 is formed on specific portions of the single crystal silicon layer 1 to mitigate an electric field, and a buffer region 13 is formed to surround the silicon island layer 1a via the trench 4 for preventing electrical interference with another lateral MOSFET or a logical circuit element provided on the identical silicon layer 1. The buffer region 13 is formed by introducing N-type impurities into the silicon layer 1 at a specific depth. An N.sup.+ diffusion layer 14 is formed in the buffer region 13 for fixing an electrical potential, and a buffer region electrode 13a is formed on the N.sup.+ diffusion layer 14.
In an ordinal operational state, for instance, the support substrate 2 and the drain electrode 7a are grounded to have an identical electric potential, and a high positive voltage is applied to the source electrode 10a. The buffer region electrode 13a is brought to be a ground potential state.
In the constitution described above, since the electric field relaxation layer 5 is composed of a semiconductor layer with an extremely low impurity concentration, the drift layer 6 and the drain contact layer 7 (P type layer), the electric field relaxation layer 5 (substantially, I type layer: intrinsic semiconductor layer), and N-wells 8a, 8b (N type layer) substantially constitute a PIN structure. According to the element structure, when a high voltage is applied across the source electrode 10a and the drain electrode 7a of the P-channel MOSFET, the applied voltage is effectively divided by a depletion layer formed in the electric field relaxation layer 5 and the silicon oxide film 3, thereby achieving a high withstand voltage.
As a result of studies to the P type LDMOS, however, the inventors of the present invention found the following problem. That is, electric field is liable to concentrate in a surface portion of the silicon island layer 1a between the source diffusion layers 10, 11 and the trench 4, due to a potential difference between the source diffusion layers 10, 11 and the buffer region 13. This can cause avalanche breakdown, and result in deterioration of the withstand voltage. To solve this problem, it is conceivable to increase an interval between the trench 4 and the source diffusion layers 10, 11; however, this constitution decreases an element density.